1. Field of the Invention
The present invention relates to an integrated circuit device, and for example, a series-connected TC parallel unit ferroelectric memory which is one of a number of types of nonvolatile semiconductor memory devices.
2. Description of the Related Art
In recent years, a series-connected TC parallel unit ferroelectric memory has been noticed as a ferroelectric memory which is one of a number of types of nonvolatile semiconductor memory devices. The series-connected TC parallel unit ferroelectric memory includes unit cells (memory cells) in each of which a lower electrode and an upper electrode of a ferroelectric capacitor (C) are connected to the source and drain of each of cell transistors (T), respectively, and which are connected in series to each other.
A series-connected TC parallel unit ferroelectric memory is subjected to a fatigue test, which will be explained with reference to FIG. 1 which is a view for use in explaining the outline of the fatigue test oF the series-connected TC parallel unit ferroelectric memory.
The series-connected TC parallel unit ferroelectric memory comprises unit blocks (memory blocks) each of which comprises eight unit cells connected in series.
As a fatigue test of a ferroelectric capacitor C1, FIG. 1 shows a case where stress voltages having different levels are alternately applied to the both ends of the ferroelectric capacitor C1. To be more specific, stress voltages are applied between a bit line BL and a plate line PL, with a block selecting signal BS for selecting a unit block set at a high level (which will be hereinafter referred to as “H”), a voltage applied to word lines WL0 and WL2 to WL7 set at “H”, and a voltage applied to a word line WL1 set at a low level (which will be hereinafter referred to as “L”). That is, an “H” or “L” voltage is applied to the bit line BL, an “L” or “H” voltage differing from the voltage applied to the bit line BL is applied to the plate line PL.
Since the voltage applied to the word lines WL0 and WL2 to WL7 is at “H”, cell transistors T0 and T2 to T7 are turned on, and the both ends of each of ferroelectric capacitors C0 and C2 to C7 are short-circuited. Thus, the both ends of each of the ferroelectric capacitors C0 and C2 to C7 have the same potential, and no stress voltages are applied to the both ends of each ferroelectric capacitor. In the ferroelectric capacitor C1 to be tested, the voltage applied to the word line WL1 is at “L”, and a cell transistor T1 is in the OFF state. Thus, the voltage applied to the bit line BL is applied to a node b of the ferroelectric capacitor C1, and the voltage applied to the plate line PL is applied to a node c of the ferroelectric capacitor C1. In this state, high and low voltages are alternately applied to the bit line BL, and also high and low voltages are alternately to the plate line PL. Thereby, high and low voltages are alternately applied to the both ends of the ferroelectric capacitor C1 to be tested, and a fatigue test is carried out (as disclosed in, e.g., Jpn. Pat. Appln. KOKAI Publication No. 2002-313100).
In the above conventional test, since during an active cycle, an address is latched, and the unit cell to be tested is fixed, it is necessary to change the voltages to be applied to the bit line BL and the plate line PL, which have relatively large parasitic capacitances. For example, in a 32-Mbits series-connected TC parallel unit ferroelectric memory, the capacitance of each of the plate lines PL is very small, compared with a ferroelectric memory in which the unit cells are not connected in series. However, even in the above series-connected TC parallel unit ferroelectric memory, each plate line PL has a parasitic capacitance of several hundred fF. Furthermore, each of the bit lines BL has a parasitic capacitance of 200 to 300 fF. It takes long time to charge/discharge such plate and bit lines having relatively large parasitic capacitances. As a result, when a high voltage is applied in an accelerated test, it also takes long time to set the voltage, and so the test takes a very long time. For example, in a fatigue test conducted in the manner shown in FIG. 1, an electric charge of 600 to 700 fF is needed in order to charge/discharge the plate line PL and bit line BL and reverse the polarization of the ferroelectric memory. In a fatigue test in which a stress voltage is applied 1010 times, if the voltages applied to the plate and bit lines change every microsecond, it takes about 24 hours to carry out a fatigue test on one specimen.